computing landscape

 

    • One notable challenge for the hardware tower is that it takes four to five years [4 to 5 years] to design and build chips and to port software to evaluate them. {“A view of the parallel computing landscape” by Krste Asanovic, Rastislav Bodík, James Demmel, Tony Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David Patterson, Koushik Sen, John Wawrzynek, David Wessel, and Katherine Yelick in the Communications of the ACM, Volume 52, Issue 10, pages 56-67, October 2009.}

    • A second challenge is that two critical pieces of system software—compilers and operating systems—have grown large and unwieldy and hence resistant to change. One estimate is that it takes a decade [10-years] for a new compiler optimization to become part of production compilers.  {“A view of the parallel computing landscape” by Krste Asanovic, Rastislav Bodík, James Demmel, Tony Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David Patterson, Koushik Sen, John Wawrzynek, David Wessel, and Katherine Yelick in the Communications of the ACM, Volume 52, Issue 10, pages 56-67, October 2009.}

    • Landscape of Parallel Computing Research:  a view from Berkeley 

       • December 18, 2006 

       • Power is expensive.  We can put more transistors on a chip than we have the power to turn on. 

       • The doubling of uniprocessor performance may now take 5 years. 

       • As chips drop below 65 nm feature sizes, they will have high soft and hard error rates. [Borkar 2005][Mukherjee et al 2005]